Cadence Design Systems, Inc. (NASDAQ: CDNS) said that ON Semiconductor has adopted Virtuoso Layout Suite for electrically aware design for real-time electrical analysis of parasitic and electromigration impact on its custom physical design implementation flow.
With Virtuoso Layout Suite EAD, ON Semiconductor circuit and layout designers will be able to significantly reduce design time and improve the energy efficiency of their designs by immediately seeing the impact of layout decisions on circuit performance.
“As the premier supplier of high-performance silicon solutions for energy-efficient electronics, ON Semiconductor believes it is important that we continue to enhance our design flows to keep pace with our customers´ demands for lower power consumption and faster time to market,” said Martin Kejhar, senior technical staff engineer and scientist at ON Semiconductor. “Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.”
Cadence enables global electronic design innovation and plays an essential role in the creation of integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. Its website is at cadence.com.