Cadence Design Systems, Inc. said it has announced a new integrated solution to significantly cut down die-package interconnect planning time from weeks to days by reducing iterations between silicon and package design teams.
The solution, built on Cadence OrbitIO technology, also shortens the time to converge on the physical interface between the die and package up to 60 percent, all within the context of the full system.
Building on its leadership position for co-design in the implementation stage, Cadence OrbitIO technology is used earlier in the design cycle to provide rapid interconnect planning of high-performance interfaces across multiple fabrics. As part of an overall co-design solution, Cadence OrbitIO technology provides seamless integration with Cadence SiP Layout and the Cadence Encounter digital implementation platform. This integrated solution allows design teams to clearly communicate design intent throughout the flow, resulting in better decision-making, fewer iterations and shorter cycle-times. It can enable fabless semiconductor or systems companies to evaluate package route feasibility, and allows them to communicate a route plan to their package design resources, whether it is to an internal group or to an outsourced assembly and test (OSAT) provider.
Cadence (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of integrated circuits and electronics. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. Its website is at cadence.com