Cadence Design Systems, Inc. (NASDAQ: CDNS) said it has announced immediate availability of DDR4 PHY IP built on TSMC´s 16nm FinFET process.
The combination of 16nm technology and Cadence´s innovative architecture helps customers realize the maximum performance of the DDR4 standard, which is specified to scale up to 3200Mbps, as compared to today´s maximum of 2133Mbps for both DDR3 and DDR4 technologies. This technology enables server, network switching, storage fabric and other systems on chip requiring high-memory bandwidth to design-in Cadence DDR4 PHY IP now and to exploit higher speed DRAMs when they become available.
The Cadence DDR4 PHY IP supports an unbuffered dual in-line memory module registered dual in-line memory module with reliability, availability, and serviceability features such as cyclic redundancy check (CRC) and data bus inversion (DBI). The new DDR4 PHY IP implements architectural innovations such as 4X clocking to minimize duty cycle distortion, multi-band power isolation for increased noise immunity, and I/O with slew rate control. The Cadence DDR4 PHY IP together with Cadence DDR4 controller are verified in silicon from TSMC´s 16nm FinFET process.
DDR4 PHY IP is silicon-tested and available now. For more information on DDR IP, visit http://ip.cadence.com/knowledgecenter/customize-main/ddr4-16ff