Cadence Design Systems, Inc. (NASDAQ: CDNS) said its digital, custom and signoff tools have received V1.0 Design Rule Manual and SPICE certification for TSMC´s 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence tools.
Cadence´s digital, custom/analog and signoff tools have been co-optimized with TSMC´s 16nm FinFET process to enable higher performance, lower power consumption and smaller area for advanced designs.
The Cadence digital RTL-to-signoff and custom/analog tools receiving the V1.0 DRM certification are: Cadence Encounter Digital Implementation System, Physical Verification System, QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Analog Design Environment and Spectre Simulator.
Cadence enables global electronic design innovation and plays an essential role in the creation of integrated circuits and electronics. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. Its website is at cadence.com.