Cadence RTL Compiler improves power, performance and area for complex chips

Cadence Design Systems, Inc. (NASDAQ: CDNS) said it has introduced the Encounter RTL Compiler version 13.1, which includes a new suite of physically aware RTL synthesis capabilities that deliver up to 15 percent improvement in power, performance and area on today´s most complex advanced node chip designs that face timing or congestion challenges.

These new capabilities are part of a production-ready physical synthesis engine that enables engineers to use physical aware techniques at the earliest phases of synthesis for better silicon results.

The new RTL synthesis capabilities include physically aware structuring, mapping, multi-bit cell inferencing and design for test that offer significant benefits for Cadence customers. Physically aware structuring and mapping can improve performance by more than 10 percent and area by more than 15 percent on complex SoCs by considering pin and register placement when deciding which micro-architectures to synthesize to, and how to balance them. Physically aware multi-bit cell inferencing can lower power by more than 10 percent by merging single registers into multi-bit registers that share a clock.

Cadence enables global electronic design innovation and plays an essential role in the creation of today´s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. More information about the company, its products, and services is available at cadence.com.

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